Circuit including vertical transistors with a conductive stack having reentrant profile

ABSTRACT

An electrical circuit includes first and second transistors. Each transistor includes a substrate and, positioned thereon, a first electrically conductive material layer including a reentrant profile functioning as a gate. First and second discrete portions of a second electrically conductive material layer are in contact with first and second portions, respectively, of a semiconductor material layer in contact with an electrically insulating material layer, both of which conform to the reentrant profile. The first and second discrete portions are source/drain and drain/source electrodes of the first and second transistors, respectively. A third electrically conductive material layer, in contact with a third portion of the semiconductor material layer, is positioned over the gate, but is not in electrical contact with it. The third electrically conductive material layer is physically separate from the electrodes of the first and second transistors and a common unconnected electrode of the first and second transistors.

CROSS REFERENCE TO RELATED APPLICATIONS

Reference is made to commonly-assigned, U.S. patent application Ser. No.13/401,934, entitled “VERTICAL TRANSISTOR ACTUATION”, filed concurrentlyherewith.

FIELD OF THE INVENTION

This invention relates generally to electrical circuits and, inparticular, to electrical circuits including vertical transistors.

BACKGROUND OF THE INVENTION

In semiconductor processing technology, planar substrate surfaces whichare horizontal with respect to a wafer surface are patterned byphotolithographic methods in combination with selective etchingprocesses. During the processing of integrated circuits, reliefs with apronounced topography are formed on the wafer or substrate surface.Typically, this type of relief includes surfaces which are inclined orvertical with respect to the substrate surface. As sizes of integratedcircuits continue to shrink, it is becoming more and more necessary topattern vertical or inclined device surfaces so as to functionallydifferentiate these devices over their vertical extent while stillmaintaining pattern alignment. Examples of these types of semiconductordevices include deep trench capacitors, stacked capacitors, and verticaltransistors.

Currently, it is not possible to put patterns directly on walls whichare vertical with respect to the substrate surface using conventionalphotolithographic techniques. Usually, vertical wall patterning of thisnature is accomplished using a suitable filler material which, whenpartially filling in a trench, acts as a mask for the portions of thewall located underneath while allowing for processing of the walls abovethe filler material. For example, when an oxide is to be depositedexclusively on vertical walls below a filler material, the oxide isfirst deposited or produced over the entire surface of the relief. Therelief or trench is initially completely filled with a suitable fillermaterial. Then, the filler material is recessed back to a depth thatjust covers the desired oxide. After uncovered sections of the oxide areremoved, the remaining filler material is removed.

Alternatively, when an oxide is to be deposited or produced only inupper regions of a vertical wall, an etching stop layer, for example, anitride layer is first provided over the entire surface of the entirerelief pattern. A different material, susceptible to directionaletching, for example, polycrystalline silicon, is used to fill therelief, and is etched back as far as the desired coverage depth of thefinal vertical oxide. After the etching stop layer is removed from theunfilled sections of the walls, an oxide is deposited or generated usinga thermal technique in the uncovered regions. Next, the oxide isanisotropically etched which removes the deposited oxide fromhorizontal. This is followed by removal of the filler material and,then, the removal of the etching stop layer.

There are deposition processes which can be used to deposit thin filmson vertical or inclined surfaces of a substrate relief. However, it isdifficult to control the thickness of the layer deposited. Typically,the thickness of the coating decreases as the depth of the reliefincreases, for example, as the length of the vertical or inclined wallincreases. As such, layers deposited using these types of depositionprocesses have considerable differences in thickness over the length ofthe relief. These types of deposition processes include plasma-enhancedchemical vapor deposition (PECVD) and diffusion-limited deposition ofsilicon oxide using tetraethyl orthosilicate (TEOS).

Vertical transistors are known. In one example of a vertical transistor,the gate region is moved vertically and one electrode of the sourcedrain combination is located over the gate region while the secondelectrode of the drain source combination is located on a lower level ofthe vertical transistor adjacent to the gate region. While this approachworks extremely well for its intended purpose, there remains anopportunity to improve aspects of the vertical transistor. For example,it is necessary to contact the electrodes of the vertical transistor ontwo different planes. This makes interconnecting the electrodes ofmultiple vertical transistors in a circuit more difficult. Conventionalmethods of interconnecting electrodes located at different heights tendto be complicated and prone to failure. In another example, the twoelectrodes used as the drain and the source do not respond or actsymmetrically due to an inherent asymmetry at the edge of the verticaltransistor. As such, vertical transistor performance often depends onwhich electrode is used as the drain and which electrode is used as thesource.

As such, there is an ongoing need to provide semiconductor devicesincluding vertical transistors having improved uniform performancecharacteristics. There is also an ongoing need to interconnecttransistors in a less complex and more reliable manner.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, an electrical circuitincludes a first transistor and a second transistor. Each of the firsttransistor and the second transistor include a substrate and a firstelectrically conductive material layer stack positioned on thesubstrate. The first electrically conductive material layer stackincludes a reentrant profile and functions as a gate. An electricallyinsulating material layer conforms to the reentrant profile of the firstelectrically conductive material layer stack and is in contact with atleast a portion of the substrate. A semiconductor material layerconforms to the reentrant profile, and is in contact with theelectrically insulating material layer. A first discrete portion of asecond electrically conductive material layer is in contact with a firstportion of the semiconductor material layer. The first discrete portionof the second electrically conductive material layer is a source/drainelectrode of the first transistor. A second discrete portion of thesecond electrically conductive material layer is in contact with asecond portion of the semiconductor material layer. The second discreteportion of the second electrically conductive material layer is adrain/source electrode of the second transistor. A third electricallyconductive material layer is in contact with a third portion of thesemiconductor material layer. The third electrically conductive materiallayer is positioned over the gate but is not in electrical contact withthe gate. The third electrically conductive material layer is physicallyseparate from the source/drain electrode of the first transistor andphysically separate from the drain/source electrode of the secondtransistor. The third electrically conductive material layer is a commonunconnected electrode of the first transistor and the second transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

In the detailed description of the example embodiments of the inventionpresented below, reference is made to the accompanying drawings, inwhich:

FIG. 1 is a schematic cross sectional view a reentrant profile verticaltransistor device including the locations of typical electricalconnections;

FIG. 2 is an electrical schematic diagram of two of the devices shown inFIG. 1;

FIG. 3 is a schematic cross sectional view of a reentrant profilevertical transistor device including the locations of electricalconnections according to an example embodiment of the invention;

FIG. 4 is an electrical schematic diagram of two of the devices shown inFIG. 3;

FIGS. 5A and 5C are graphs showing performance Id-Vd curvecharacteristics for the vertical transistor shown in FIG. 1 for twosource drain connections shown in FIGS. 5B and 5D, respectively, thecurves representing increasing gate voltage in 0.25 Volt increments; and

FIGS. 6A and 6C are graphs showing performance Id-Vd curvecharacteristics for the vertical transistor shown in FIG. 3 for twosource drain connections shown in FIGS. 6B and 6D, respectively, thecurves representing increasing gate voltage in 0.25 Volt increments.

DETAILED DESCRIPTION OF THE INVENTION

The present description will be directed in particular to elementsforming part of, or cooperating more directly with, apparatus inaccordance with the present invention. It is to be understood thatelements not specifically shown or described may take various forms wellknown to those skilled in the art. In the following description anddrawings, identical reference numerals have been used, where possible,to designate identical elements.

The example embodiments of the present invention are illustratedschematically and not to scale for the sake of clarity. One of theordinary skills in the art will be able to readily determine thespecific size and interconnections of the elements of the exampleembodiments of the present invention.

Referring to FIG. 1, an example embodiment of a vertical transistors 90,shown in cross section, which is included in the electrical circuit ofthe present invention or included in the semiconductor device actuationmethod of the present invention is shown. Vertical transistors 90include a reentrant profile 80. A substrate 100 can be any material orcombination of materials as long as it fulfills the function of holdingor supporting the layers on it and not acting as a short site for thegate and source/drain electrodes. Onto this substrate 100, anelectrically conductive gate 110 is patterned with an appropriatethickness for the desired gate length of the vertical transistors 90.The gate 110 is conductive to allow the fields to be generated whichallow the transistors 90 to actuate. Reentrant profile 80 is created bymaterial layer 120 that is located on or above the electricallyconductive gate 110 and is preferably a conductive material. Its mainfunction, however, is to provide an overhang to shadow a portion of thesubstrate 100 and any intervening layers (layer 110, for example)underneath the overhang. Conductive gate 100 and material layer 120 forma first electrically conductive material layer stack in this exampleembodiment of vertical transistors 90.

The coatings of dielectric material 130 and semiconductor material 140are conformal and therefore portions of both are shadowed when anelectrically conducting material layer or layers (forming electrodes150, 160, and 170) are deposited by a directional (for example, ananisotropic) deposition process such as thermal evaporation orsputtering. Typically, electrodes 150, 160, and 170 are discreteportions of the same material layer. Electrode 160 is physicallyseparated from electrodes 150 and 170 due to its position on the firstelectrically conductive material layer stack.

FIG. 1 also shows where conventional electrical connections are made tothe different electrically conductive materials. The gate electricalconnection 180 is connected to the electrically conductive gate 110. Thesource or drain electrical connection 190 is connected to theelectrically conducting electrode 160 and the other connection, thedrain or source electrical connection 200, is connected to theelectrically conducting electrode 170. This yields the three necessaryconnections for a standard transistor. The other electrically conductingelectrode 150 is left unconnected. One should realize that, due to thesymmetry, either electrically conducting electrode 150 or 170 can beused interchangeably as the drain or source electrical connection 200,with the other left unconnected.

FIG. 2 shows an electrical schematic diagram of the vertical transistorsshown in FIG. 1 using conventional electrical connections. While it isuseful to connect these transistors into a circuit in the standard way,it requires one to attach an electrical connection to the electrode 160on top of the vertical transistors. This not only adds height, but mayalso decrease the robustness of the vertical transistors because thematerials of the gate may not be as flexible as the material of thesupport. Furthermore, the complexity of the electrical connects isincreased because special interconnect circuitry is often used toconnect the top of the transistor to the surrounding substrate plane.Also, the overhang of the reentrant profile might not be symmetric withthe bottom of the transistors leading to an asymmetry in the electricalresponse of the transistors formed on either side of the gate.

Referring to FIG. 3, an example embodiment of the vertical transistorsof FIG. 1 is shown in cross section and includes the electricalconnections that facilitate the present inventions. The material layersof the vertical transistors 90 shown in FIG. 3 are the same as thoseshown FIG. 1. The electrical connections 180, 190, 200, however, aredifferent. In FIG. 3, electrical connection 190 is connected to thesymmetric electrically conducting electrode 150. There is no electricalconnection made to the electrically conducting electrode 160 locatedabove the electrically conductive gate 110.

Additional example embodiments of vertical transistors that can beincluded in the circuit of the present invention or in the actuationmethod of the present invention include, for example, U.S. Pat. No.7,985,684 B1, issued to Tutt et al., on Jul. 26, 2011; U.S. Pat. No.7,923,313 B1, issued to Tutt et al., on Apr. 12, 2011; U.S. patentapplication Ser. No. 13/218,482, filed by Nelson and Tutt, on Aug. 26,2011; and U.S. patent application Ser. No. 12/986,241, filed by Tutt andNelson, on Jan. 7, 2011, the disclosures of which are incorporatedherein in their entirety. For example, in some embodiments of thepresent invention, the electrically insulating material layer is a firstelectrically insulating material layer and vertical transistors 90include a second electrically insulating material layer positioned inbetween the first electrically conductive material layer stack and thethird electrically conductive material layer. In other exampleembodiments of the invention, the first electrically conductive materiallayer stack includes a single material layer with the reentrant profilein the single material layer. In another example embodiment of theinvention, the first electrically conductive material layer stackincludes a plurality of material layers with the reentrant profile beingin one or a combination of the plurality of material layers.

When the vertical transistor includes a second electrically insulatingmaterial layer positioned in between the first electrically conductivematerial layer stack and the third electrically conductive materiallayer, typically, the second electrically insulating material layer is alow k dielectric material layer. The low k dielectric material layer caninclude an organic material, for example, one of a photoresist and apolymer. In some example embodiments, when the second electricallyinsulating material layer is a low k dielectric material layer, thefirst electrically insulating material layer can be a high k dielectricmaterial layer.

Actuation of a semiconductor device is accomplished by providing avertical transistors 90 as shown in FIG. 3. A voltage is applied betweenthe first discrete portion of the second electrically conductivematerial layer (for example, electrode 150) and the second discreteportion of the second electrically conductive material layer (forexample, electrode 170). A voltage is applied to the first electricallyconductive material layer stack (for example, gate 110 and materiallayer 120) to modulate a resistance between the first discrete portionof the second electrically conductive material layer and the seconddiscrete portion of the second electrically conductive material layer.

Referring to FIG. 4, an electrical schematic diagram of a doubletransistor configuration including the vertical transistors shown inFIG. 3 using the electrical connections shown in FIG. 3 to connect thevertical transistors into a circuit is shown. As shown in FIG. 4, thetwo transistors have a common unconnected electrode and the gates aretied together and simultaneously energized by the gate electricalconnection 180. The drain and source electrodes are symmetric andtherefore the source (or drain) electrical connection 190 and drain (orsource) electrical connection 200 can be interchanged in the circuit.The first and second transistors are electrically connected on a singleplane which helps to reduce the electrical wiring needed for the circuitwhile maintaining performance uniformity of the transistors.

Experimental Results

To show the utility of this approach, vertical transistors were made andthe connection made using the following process.

A layer of 590 nm of molybdenum was deposited via sputtering on a 62.5mm square glass substrate. On top of this, a 120 nm conductive aluminumzinc oxide (AZO) layer using the S-ALD process described in U.S. Pat.No. 7,413,982 and the S-ALD apparatus described in U.S. Pat. No.7,456,429 with the organo-metallic precursors dimethylaluminumisopropoxide, diethyl zinc and an oxygen source of water with an inertcarrier gas of nitrogen.

A patterned layer of photoresist was formed by spin coating at 3000 rpmMicroposit S1813 resist (Rohm and Haas Electronic Materials LLC,Marlborough, Mass.) placed on a hot plate for 60 sec at 110 degreesCelsius and then exposed through a glass/chromium contact mask includinglines for 60 seconds on a Cobilt mask aligner (Cobilt model CA-419 fromComputervision Corporation, Sunnyvale, Calif.) The sample was thendeveloped for 60 seconds in Microposit MF-319 developer (Rohm and HaasElectronic Materials LLC, Marlborough, Mass.) and rinsed for 1 minute inDI water.

The AZO layer was etched in dilute nitric acid for 35 seconds, leavingAZO under the photoresist lines. The conductive molybdenum was thenplasma etched with 0.3 torr SF6 at 200 W for 7 minutes using a PEII-Aplasma etcher (Technics West Inc.). The photoresist was removed withacetone, then rinsed in HPLC grade isopropanol, and allowed to dry.

The substrate was then coated with a layer 15 nm thick of aluminum oxideconformally using the S-ALD process at 200 degrees Celsius with theorgano-metallic precursors trimethyl aluminum and water with an inertcarrier gas of nitrogen.

The substrate was then coated with a 12 nm layer of zinc oxide againusing the S-ALD process at 200 degrees Celsius using the precursorsdiethyl zinc and water and nitrogen as the carrier gas.

The electrodes were applied by evaporation. Aluminum, about 70 nm thick,was evaporated through a shadow mask consisting of rectangular holeswhich run perpendicular to and completely cross each line on thesubstrate.

Testing of the transistor was accomplished by using a probe station tocontact the aluminum on top of the molybdenum gate lines, the aluminumon one or both sides of the line and the molybdenum metal which acts asthe gate.

Referring to FIGS. 5A-5D, measurements were taken on a verticaltransistor including the electrical connections shown in FIG. 1. Thecurrent versus voltage of the two configurations of connecting thesource electrode 210 above the gate electrode 230 (FIG. 5B) or beside it(FIG. 5D), with the drain electrode 220 in the other location, weremeasured and are plotted in FIGS. 5A and 5C, respectively. It can beclearly seen that there is an asymmetry between the electrical resultsof the two different electrical connections.

Referring to FIGS. 6A-6D, measurements were taken on a verticaltransistor including the electrical connections of the present inventionand shown in FIG. 3. The current versus voltage of two configurations ofconnecting the source electrode 210 on one side of the gate electrode230 (FIG. 6B) or the other side (FIG. 6D), with the drain electrode 220in the other location, were measured and are plotted in FIGS. 6A and 6C,respectively. It can be clearly seen that the symmetry of the twoconnections yields a virtually identical current voltage response. Thecurrent carrying capacity is slightly reduced, relative to the controlconnections, but that can be correspondingly modified by making ashorter channel length to give the desired current capacity. It shouldalso be noted that a short circuit across one of the transistors, whilechanging the circuit response, does not cause a failure. The circuit isnow also more robust because the connections are now all on the sameplane allowing less complex circuit interconnection.

The invention has been described in detail with particular reference tocertain preferred embodiments thereof, but it will be understood thatvariations and modifications can be effected within the scope of theinvention.

PARTS LIST

-   80 Reentrant profile-   90 Vertical transistors-   100 Substrate-   110 Electrically conductive gate-   120 Reentrant profile material-   130 Dielectric material-   140 Semiconducting material-   150 Electrically conducting electrode-   160 Electrically conducting electrode-   170 Electrically conducting electrode-   180 Gate electrical connection-   190 Source or drain electrical connection-   200 Drain or source electrical connection-   210 Source electrode-   220 Drain electrode-   230 Gate electrode

The invention claimed is:
 1. An electrical circuit comprising: a first transistor and a second transistor, each of the first transistor and the second transistor including: a substrate; an first electrically conductive material layer stack positioned on the substrate, the first electrically conductive material layer stack including a reentrant profile, the first electrically conductive material layer stack being a gate; an electrically insulating material layer that conforms to the reentrant profile of the first electrically conductive material layer stack, and is in contact with at least a portion of the substrate; a semiconductor material layer that conforms to the reentrant profile, and is in contact with the electrically insulating material layer; a second electrically conductive material layer, a first discrete portion of the second electrically conductive material layer in contact with a first portion of the semiconductor material layer, the first discrete portion of the second electrically conductive material layer being a source/drain electrode of the first transistor, a second discrete portion of the second electrically conductive material layer in contact with a second portion of the semiconductor material layer, the second discrete portion of the second electrically conductive material layer being a drain/source electrode of the second transistor; and a third electrically conductive material layer in contact with a third portion of the semiconductor material layer, the third electrically conductive material layer being positioned over the gate but not in electrical contact with the gate, the third electrically conductive material layer being physically separate from the source/drain electrode of the first transistor and physically separate from the drain/source electrode of the second transistor; wherein the third electrically conductive material layer is a common unconnected electrode of the first transistor and the second transistor.
 2. The circuit of claim 1, the electrically insulating material layer being a first electrically insulating material layer, the first transistor and the second transistor further comprising: a second electrically insulating material layer positioned in between the first electrically conductive material layer stack and the third electrically conductive material layer.
 3. The circuit of claim 2, wherein the second electrically insulating material layer is a low k dielectric material layer.
 4. The circuit of claim 3, wherein the low k dielectric material layer includes an organic material.
 5. The circuit of claim 4, wherein the organic material includes one of a photoresist and a polymer.
 6. The circuit of claim 3, wherein the first electrically insulating material layer is a high k dielectric material layer. 